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<title>Buffer</title>
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<h1><img align="center" height="32" width="32" src="../../../icons/bufferGate.gif"> <em>Buffer</em></h1>

<p><table>
<tr><td><strong>Library:</strong></td>
	<td><a href="index.html">Gates</a></td></tr>
<tr><td><strong>Introduced:</strong></td>
	<td>2.0 Beta 1</td></tr>
<tr><td valign="top"><strong>Appearance:</strong></td>
	<td valign="top"><img src="../../../img-libs/buffer.png"></td></tr>
</table></p>

<h2>Behavior</h2>

<p>The buffer simply passes through to its right output whatever input
it receives on the left side.
The truth table for a one-bit buffer is the following.</p>
<center><table>
<tr><th><var>x</var></th><th>out</th></tr>
<tr><td align="center">0</td><td align="center">0</td></tr>
<tr><td align="center">1</td><td align="center">1</td></tr>
</table></center>
<p>If the input is unspecified (i.e., floating), then the output will also be
unspecified - unless the "Gate Output When Undefined" option is "Error for
undefined inputs," in which case the output is an error. If the input is an
error value, then the output will also be.</p>

<p>Buffers are the most useless of the gate components
provided in Logisim; its presence in the Gates library is just as much a
matter of completeness (a component for each possible
one-input truth table) as it is a matter of providing useful
functionality. Still, it can be occasionally useful to ensure that
values propagate in only one direction along a wire.</p>

<h2>Pins (assuming component faces east)</h2>

<dl>

<dt>West edge (input, bit width according to Data Bits attribute)
<dd>The input into the component.

<dt>East edge (output, bit width according to Data Bits attribute)
<dd>The output, which always matches the input into the left side.

</dl>

<h2>Attributes</h2>

<p>When the component is selected or being added,
Alt-0 through Alt-9 alter its <q>Data Bits</q> attribute
and the arrow keys alter its <q>Facing</q> attribute.</p>

<dl>

<dt>Facing</dt>
<dd>The direction of the component (its output relative to its input).</dd>

<dt>Data Bits</dt>
<dd>The bit width of the component's inputs and outputs.</dd>

<dt>Output Value</dt>
<dd>Indicates how false and true results should be translated into output values.
By default, false is indicated by a low voltage (0) and true by a high voltage (1),
but one or the other can be replaced by a high-impedance (<q>floating</q>) value
instead. This allows wired-or and wired-and connections, as illustrated in
the <a href="basic.html">AND/OR/NAND/NOR Gate documentation</a>.</dd>

<dt>Label</dt>
<dd>The text within the label associated with the gate.</dd>

<dt>Label Font</dt>
<dd>The font with which to render the label.</dd>

</dl>

<h2>Poke Tool Behavior</h2>

<p>None.</p>

<h2>Text Tool Behavior</h2>

<p>Allows the label associated with the gate to be edited.</p>

<p><a href="../index.html">Back to <em>Library Reference</em></a></p>

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